About:

 

A question that is commonly asked is “Why do I need a Patched DSDT or SSDT for my system when I have read and been told that I do not need one?” To start, this is a lie – Every system regardless of manufacture needs the ACPI Tables patched by either directly patching the DSDT or using a SSDT to do so. Otherwise, many items on a motherboard will be broken and/or not enabled, not to mention their services that will not load due to lack of required code.

The following code is the SSDT found on the Haswell DMG for the Gigabyte Z97X UD7 TH. The code is 572 Lines. That is a lot of lines of code for something that you were told did not need patching. This is the minimum code needed for this board.

All we ask here is to not believe the lies that others state constantly as all the proof is before you:

DefinitionBlock ("SSDT.aml", "SSDT", 1, "Test", "1", 0x00003000)
{
 External (\_PR_.CPU7)
 External (\_PR_.CPU6)
 External (\_PR_.CPU5)
 External (\_PR_.CPU4)
 External (\_PR_.CPU3)
 External (\_PR_.CPU2)
 External (\_PR_.CPU1)
 External (\_PR_.CPU0)
 External (\_SB_.SLPB)
 External (_SB_.PCI0.GLAN, DeviceObj)
 External (_SB_.PCI0.PEG0.PEGP, DeviceObj)
 Method (MAIN, 0, NotSerialized)
 {
 Store ("dsdt.dsl", Debug)
 Store (0x11, Debug)
 Store ("Wed Oct 1 06:40:30 2014", Debug)
 Store ("Haswell SSDT By RampageDev All Rights Reserved", Debug)
 Store ("For Use With Intel Motherboards Only", Debug)
 Store ("Report Issues With This SSDT To: AKern@RampageDev.com", Debug)
 }
 Method (_SB.PCI0.SAT0._DSM, 4, NotSerialized)
 {
 If (LEqual (Arg2, Zero))
 {
 Return (Buffer (One)
 {
 0x03
 })
 }
 Return (Package (0x06)
 {
 "device-id", 
 Buffer (0x04)
 {
 0x02, 0x8C, 0x00, 0x00
 }, 
 "compatible", 
 "pci8086,8c02", 
 "IOName", 
 "pci8086,8c02"
 })
 }
 Method (_SB.PCI0.LPCB._DSM, 4, NotSerialized)
 {
 If (LEqual (Arg2, Zero))
 {
 Return (Buffer (One)
 {
 0x03
 })
 }
 Return (Package (0x06)
 {
 "device-id", 
 Buffer (0x04)
 {
 0x11, 0x28, 0x00, 0x00
 }, 
 "compatible", 
 "pci8086,2811", 
 "IOName", 
 "pci8086,2811"
 })
 }
 Method (_SB.PCI0.HDEF._DSM, 4, NotSerialized)
 {
 If (LEqual (Arg2, Zero))
 {
 Return (Buffer (One)
 {
 0x03
 })
 }
 Return (Package (0x06)
 {
 "layout-id", 
 Buffer (0x04)
 {
 0x01, 0x00, 0x00, 0x00
 }, 
 "PinConfigurations", 
 Buffer (Zero) {}, 
 "hda-gfx", 
 Buffer (0x0A)
 {
 "onboard-3"
 }
 })
 }
 Method (_SB.PCI0.GFX0._DSM, 4, NotSerialized)
 {
 If (LEqual (Arg2, Zero))
 {
 Return (Buffer (One)
 {
 0x03
 })
 }
 Return (Package (0x0C)
 {
 "hda-gfx", 
 Buffer (0x0A)
 {
 "onboard-2"
 }, 
 "AAPL,ig-platform-id", 
 Buffer (0x04)
 {
 0x03, 0x00, 0x22, 0x0D
 }, 
 "device-id", 
 Buffer (0x04)
 {
 0x22, 0x0D, 0x00, 0x00
 }, 
 "subsystem-id", 
 Buffer (0x04)
 {
 0x1A, 0x01, 0x00, 0x00
 }, 
 "subsystem-vendor-id", 
 Buffer (0x04)
 {
 0x6B, 0x10, 0x00, 0x00
 }, 
 "compatible", 
 "pci8086,0d22"
 })
 }
 Scope (_SB.PCI0.PEG0.PEGP)
 {
 OperationRegion (PEGH, PCI_Config, Zero, 0x40)
 Field (PEGH, ByteAcc, NoLock, Preserve)
 {
 VID0, 16, 
 DID0, 16
 }
 Method (_DSM, 4, NotSerialized)
 {
 If (LEqual (Arg2, Zero))
 {
 Return (Buffer (One)
 {
 0x03
 })
 }
 Return (Package (0x0C)
 {
 "AAPL,slot-name", 
 Buffer (0x07)
 {
 "Slot-2"
 }, 
 "@0,connector-type", 
 Buffer (0x04)
 {
 0x00, 0x08, 0x00, 0x00
 }, 
 "@1,connector-type", 
 Buffer (0x04)
 {
 0x00, 0x08, 0x00, 0x00
 }, 
 "@2,connector-type", 
 Buffer (0x04)
 {
 0x00, 0x08, 0x00, 0x00
 }, 
 "@3,connector-type", 
 Buffer (0x04)
 {
 0x00, 0x08, 0x00, 0x00
 }, 
 "hda-gfx", 
 Buffer (0x0A)
 {
 "onboard-1"
 }
 })
 }
 }
 Scope (_SB.PCI0.GLAN)
 {
 OperationRegion (GPIO, SystemIO, 0x0800, 0x06)
 Field (GPIO, ByteAcc, NoLock, Preserve)
 {
 GO01, 8, 
 GO02, 8, 
 GO03, 8, 
 GO04, 8, 
 GO05, 8, 
 GP45, 1, 
 GP9, 1
 }
 Method (EWOL, 1, NotSerialized)
 {
 If (LEqual (Arg0, One))
 {
 Or (GP9, One, GP9)
 }
 Else
 {
 And (GP9, Zero, GP9)
 }
 If (LEqual (Arg0, GP9))
 {
 Return (Zero)
 }
 Else
 {
 Return (One)
 }
 }
 Method (_DSM, 4, NotSerialized)
 {
 If (LEqual (Arg2, Zero))
 {
 Return (Buffer (One)
 {
 0x03
 })
 }
 Return (Package (0x0A)
 {
 "AAPL,slot-name", 
 Buffer (0x09)
 {
 "Internal"
 }, 
 "built-in", 
 Buffer (One)
 {
 0x01
 }, 
 "device_type", 
 "Ethernet Controller", 
 "model", 
 "Intel i217V", 
 "name", 
 "Ethernet Controller"
 })
 }
 }
 Device (_SB.PCI0.LBCB.EC)
 {
 Name (_HID, EisaId ("PNP0C09"))
 Name (_UID, Zero)
 Name (_CRS, ResourceTemplate ()
 {
 IO (Decode16,
 0x0062, // Range Minimum
 0x0062, // Range Maximum
 0x00, // Alignment
 0x01, // Length
 )
 IO (Decode16,
 0x0066, // Range Minimum
 0x0066, // Range Maximum
 0x00, // Alignment
 0x01, // Length
 )
 })
 Name (_GPE, 0x17)
 OperationRegion (PLMT, SystemIO, 0x0310, 0x0A)
 Field (PLMT, WordAcc, Lock, Preserve)
 {
 CPLT, 8, 
 IGPS, 8, 
 MPLT, 8, 
 CFIL, 8, 
 EGPS, 8
 }
 Name (ECOK, Zero)
 OperationRegion (ECOR, EmbeddedControl, Zero, 0xFF)
 Field (ECOR, ByteAcc, Lock, Preserve)
 {
 ECVS, 8, 
 Offset (0x02), 
 Offset (0x03), 
 G3HT, 1, 
 Offset (0x04), 
 WBCB, 1, 
 DSLP, 1, 
 Offset (0x05), 
 Offset (0x06), 
 WKRS, 8, 
 Offset (0x10), 
 ECSS, 8, 
 PLIM, 8, 
 ALB0, 8, 
 ALB1, 8, 
 WTLB, 8, 
 WTMB, 8, 
 Offset (0x20), 
 SPTR, 8, 
 SSTS, 8, 
 SADR, 8, 
 SCMD, 8, 
 SBFR, 256, 
 SCNT, 8, 
 SAAD, 8, 
 SAD0, 8, 
 SAD1, 8, 
 SMUX, 8, 
 Offset (0x60), 
 ELSW, 1, 
 EACP, 1, 
 ECDI, 1, 
 ENMI, 1, 
 Offset (0x61), 
 EMHP, 1, 
 Offset (0x62), 
 Offset (0x63), 
 Offset (0x64), 
 SWLO, 1, 
 SWLC, 1, 
 SWAI, 1, 
 SWAR, 1, 
 SWCI, 1, 
 SWCE, 1, 
 SWMI, 1, 
 SWMR, 1, 
 SWPB, 1, 
 SWGP, 1, 
 SWPM, 1, 
 SWWT, 1, 
 SWLB, 1, 
 Offset (0x66), 
 Offset (0x67), 
 Offset (0x68), 
 EWLO, 1, 
 EWLC, 1, 
 EWAI, 1, 
 EWAR, 1, 
 EWCI, 1, 
 EWCE, 1, 
 EWMI, 1, 
 EWMR, 1, 
 EWPB, 1, 
 EWGP, 1, 
 EWPM, 1, 
 ENWT, 1, 
 EWLB, 1, 
 Offset (0x6A), 
 Offset (0x6B), 
 Offset (0x6C), 
 LWLO, 1, 
 LWLC, 1, 
 LWAI, 1, 
 LWAR, 1, 
 LWCI, 1, 
 LWCE, 1, 
 LWMI, 1, 
 LWMR, 1, 
 LWPB, 1, 
 LWGP, 1, 
 LWPM, 1, 
 LWWT, 1, 
 LWLB, 1, 
 Offset (0x6E), 
 Offset (0x6F), 
 Offset (0x70)
 }
 Field (ECOR, ByteAcc, Lock, Preserve)
 {
 Offset (0x03), 
 G3AD, 1, 
 BLOD, 1, 
 S4WE, 1, 
 APWC, 1, 
 Offset (0x04), 
 Offset (0x6C), 
 LWE0, 8, 
 LWE1, 8, 
 LWE2, 8, 
 LWE3, 8
 }
 Field (ECOR, ByteAcc, Lock, Preserve)
 {
 Offset (0x24), 
 SBDW, 16, 
 Offset (0x46), 
 SADW, 16
 }
 Method (WAKE, 0, NotSerialized)
 {
 If (ECOK)
 {
 Return (WKRS)
 }
 Else
 {
 Return (Zero)
 }
 }
 Method (_Q40, 0, NotSerialized)
 {
 }
 Method (_Q5A, 0, NotSerialized)
 {
 Notify (\_SB.SLPB, 0x80)
 }
 Method (_Q80, 0, NotSerialized)
 {
 Notify (\_PR.CPU0, 0x80)
 Notify (\_PR.CPU1, 0x80)
 Notify (\_PR.CPU2, 0x80)
 Notify (\_PR.CPU3, 0x80)
 Notify (\_PR.CPU4, 0x80)
 Notify (\_PR.CPU5, 0x80)
 Notify (\_PR.CPU6, 0x80)
 Notify (\_PR.CPU7, 0x80)
 Store (EGPS, Local0)
 If (LEqual (\_SB.PCI0.PEG0.PEGP.VID0, 0x10DE))
 {
 If (LEqual (\_SB.PCI0.PEG0.PEGP.DID0, 0x0FEA))
 {
 If (LLessEqual (Local0, 0x03))
 {
 Notify (\_SB.PCI0.PEG0.PEGP, 0xD1)
 }
 Else
 {
 If (LAnd (LGreater (Local0, 0x03), LLessEqual (Local0, 0x08)))
 {
 Notify (\_SB.PCI0.PEG0.PEGP, 0xD2)
 }
 If (LAnd (LGreater (Local0, 0x08), LLessEqual (Local0, 0x0D)))
 {
 Notify (\_SB.PCI0.PEG0.PEGP, 0xD3)
 }
 If (LAnd (LGreater (Local0, 0x0D), LLessEqual (Local0, 0x11)))
 {
 Notify (\_SB.PCI0.PEG0.PEGP, 0xD4)
 }
 If (LGreater (Local0, 0x11))
 {
 Notify (\_SB.PCI0.PEG0.PEGP, 0xD5)
 }
 }
 }
 Else
 {
 If (LLessEqual (Local0, 0x02))
 {
 Notify (\_SB.PCI0.PEG0.PEGP, 0xD1)
 }
 Else
 {
 If (LAnd (LGreater (Local0, 0x02), LLessEqual (Local0, 0x05)))
 {
 Notify (\_SB.PCI0.PEG0.PEGP, 0xD2)
 }
 If (LAnd (LGreater (Local0, 0x05), LLessEqual (Local0, 0x08)))
 {
 Notify (\_SB.PCI0.PEG0.PEGP, 0xD3)
 }
 If (LAnd (LGreater (Local0, 0x08), LLessEqual (Local0, 0x0B)))
 {
 Notify (\_SB.PCI0.PEG0.PEGP, 0xD4)
 }
 If (LGreater (Local0, 0x0B))
 {
 Notify (\_SB.PCI0.PEG0.PEGP, 0xD5)
 }
 }
 }
 }
 }
 Method (_REG, 2, NotSerialized)
 {
 If (LOr (LEqual (Arg0, 0x03), Zero))
 {
 Store (Arg1, ECOK)
 If (LEqual (Arg1, One))
 {
 Store (Zero, ECSS)
 }
 }
 }
 }
 Device (_SB.PCI0.PEG0.HDAU)
 {
 Name (_ADR, One)
 OperationRegion (HDAH, PCI_Config, Zero, 0x40)
 Field (HDAH, ByteAcc, NoLock, Preserve)
 {
 VID0, 16, 
 DID0, 16
 }
 Method (_DSM, 4, NotSerialized)
 {
 If (LEqual (Arg2, Zero))
 {
 Return (Buffer (One)
 {
 0x03
 })
 }
 Return (Package (0x02)
 {
 "hda-gfx", 
 Buffer (0x0A)
 {
 "onboard-1"
 }
 })
 }
 }
 Device (_SB.VSND)
 {
 Name (_HID, EisaId ("APP0007"))
 Name (_CID, "virtual-sound")
 Name (_STA, 0x0B)
 Method (_DSM, 4, NotSerialized)
 {
 If (LEqual (Arg2, Zero))
 {
 Return (Buffer (One)
 {
 0x03
 })
 }
 Return (Package (0x0A)
 {
 "AAPL,slot-name", 
 Buffer (0x09)
 {
 "Internal"
 }, 
 "device_type", 
 "Security Controller", 
 "model", 
 "Haswell SSDT By RampageDev All Rights Reserved", 
 "name", 
 "Security Controller", 
 "hda-gfx", 
 Buffer (0x0A)
 {
 "onboard-4"
 }
 })
 }
 }
 Device (_SB.PCI0.SBUS.BUS0)
 {
 Name (_CID, "smbus")
 Name (_ADR, Zero)
 Device (BLC0)
 {
 Name (_ADR, 0x57)
 Name (_CID, "diagsvault")
 Method (_DSM, 4, NotSerialized)
 {
 If (LEqual (Arg2, Zero))
 {
 Return (Buffer (One)
 {
 0x03
 })
 }
 Return (Package (0x02)
 {
 "address", 
 0x57
 })
 }
 }
 }
}

9 Comments on "What Is In An SSDT Or Patched DSDT? I Was Told I Do Not Need One?"

  1. Thanks for making that clear. I´ve heard, there are other sources/pages on the web where you being told this kind of lies…. and where you get pre-defined m….fail software.

    Reply
  2. Another thing I encounter often when trying to help someone (I often ask for an IOReg and a DSDT) is “I don’t have a DSDT.” When you use you-know-who’s post-installation tool, not installing a DSDT is referred to as a “DSDT-free” installation… This is probably where a lot of the confusion comes from.

    Reply
  3. Hi Andrew,

    I have a working Yosemite hackintosh based on a different source which I haven’t used any SSDT’s since my MB works OOB as stated at Tony’s guide. Now I kept reading here in your site that I have to use SSDTs regardless of my hardware components. Should I reinstall from scratch or just copy those SSDTs to where it should be copied?

    Thanks.

    Reply
  4. So I have to fresh install?

    Reply
  5. If were were to do all edits to the DSDT and do not need power management, is there any case where we would need to have a modified SSDT?

    Looking to make onboard eth and audio work on a GA-B75M-D3P

    Reply

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About Andrew Kern